This invention relates to semiconductor Field Effect Transistor (FET) devices with Raised Source/Drain (RSD) junctions and manufacturing methods therefor, and more particularly, RSD Metal Insulator Semiconductor (MIS) or Metal Oxide Semiconductor (MOS) FET devices including Complementary MISFET and MOSFET devices and methods of manufacture thereof wherein spacers are formed on the sidewalls of a gate conductor.
As integrated circuit dimensions inexorably become smaller and smaller thereby reducing the scale of FET devices, we have found that making electrical and mechanical contact of studs extending from an upper surface of a device at junctions with the RSD source and drains regions of devices becomes increasingly more difficult. To make proper connections to the RSD regions, it is required to etch via holes down to a predetermined depth below that upper surface without missing the target laterally in whole or in part.
An important priority is to assure that the contacts made through via holes connect to conductive materials on the surfaces of RSD regions and not to lateral dielectric materials, i.e. electrical insulators. However in the past the practice has been to form sidewall spacers on the sidewalls of the gate electrodes of the FET devices, with the RSD regions juxtaposed with the sidewall spacers on the opposite sides thereof from the gate electrodes. We have found that the presence of the sidewall spacers which are composed of dielectric materials in locations where via holes might be etched because of minor deviations of the location thereof from the desired location will lead to making partial or total connection to the spacer composed of a dielectric material instead of the electrically conductive contact surface on top of the RSD regions.
A prior art approach to forming RSD regions in FET devices which illustrates the problems described above is shown in FIG. 2, U.S. Pat. No. 5,915,183 of Gambino et al. entitled “Raised Source/Drain using Recess Etch of Polysilicon” shows a MOS FET semiconductor device 6 comprising a semiconductor substrate 8 doped with p-type dopant. Raised Shallow Trench Isolation (STI) regions 16 filled with silicon dioxide (SiO2) are formed on the periphery of the surface of the semiconductor substrate 8. A gate dielectric layer 30 is formed on the central portion of the surface of the substrate 8 and a gate electrode 72 is formed on the gate dielectric layer 30 in a gate electrode trench 20, centered between the STI regions 16 which are on the distal borders of the portion of device 6. Two source/drain extensions 42, which are doped with n-type dopant, are formed in the surface of the substrate 8 aside from the gate electrode 72. Raised source/drain (RSD) regions 74 are formed on the surface of the substrate 8 spaced away from the gate electrode 72 by the width of a set of conventional sidewall spacers 40 composed of silicon nitride (Si3N4.) A set of salicide layers 70 cover the RSD regions 74 and the gate electrode 72. The conventional spacers 40, composed of silicon nitride, are wide enough to provide a very substantial reduction in the width of the RSD regions 74 on both the edges proximate to the gate electrode 72 and the edges proximate to the raised STI trenches 16. As a function of the continuing trend towards the reduction in the dimensional scale of FET devices, the reduction in the width of the RSD regions 74 results in ever increasing difficulty in making sufficiently conductive and adequately aligned electrical connections thereto in vias formed in structure of a large scale semiconductor product.
The process described in Gambino et al for manufacture of the device 6 of FIG. 2 starts with formation of an original silicon nitride layer (12) over a pad oxide layer (14) formed on top of the semiconductor substrate 8. A pair of raised STI regions 16 filled with isolation material are formed on the edges of the original silicon nitride layer (12.) Then a gate electrode trench 20 reaching down through the silicon nitride layer (12) and is formed followed by removal of the exposed portion of the pad oxide layer (14) and deposition into the gate electrode trench 20 of both a gate dielectric layer 30 and a gate electrode layer (32), composed of polysilicon. Next, the gate electrode layer (32) is planarized to provide the planar gate electrode 72 seen in FIG. 2 herein followed by removal of the remainder of the original silicon nitride layer (12.) Thereafter source/drain extensions 42 are formed in the substrate 8 and sidewall spacers 40 are formed on the sidewalls of gate electrode 72 thereby defining source/drain recesses between sidewalls spacers 40 on the exposed sidewalls of the gate electrode 72 and on the exposed sidewalls of the STI regions 16. Next a blanket layer 74 of intrinsic polysilicon is deposited thereby filling the source/drain recesses followed by planarizing using CMP (Chemical Mechanical Polishing) combined with etching to form the RSD regions 74. Thus, the edges of the RSD regions 74 are defined by the sidewall spacers 40 and the raised STI regions 16. A salicide layer over 70 is formed on the top surfaces of both the gate conductor 72 and the RSD regions 74. Conventional polysilicon deposition, CMP, and recess steps are employed to form junctions to the RSD regions 74. A significant problem with the method and device of Gambino U.S. Pat. No. 5,915,183 is that it is difficult to make the connections of the junctions to the RSD regions 74 of the device 6 because of the narrowing thereof attributable to the widths of the sidewall spacers 40. An object of this invention is to overcome that problem.
U.S. Pat. No. 6,566,208 of Pan et al. entitled “Method to Form Elevated Source/Drain Using Poly Spacer” describes a method for forming a sub-quarter micron MOS FET having an elevated source/drain structure. A gate dielectric and a gate electrode are formed over a semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly doped regions using the gate electrode as a mask. Then thin, dielectric, sidewall spacers from 25 Å to 200 Å thick are formed on sidewalls of the gate electrode. A thicker, heavily doped, polysilicon layer from 500 Å to 4000 Å thick is deposited overlying the semiconductor substrate, gate electrode, and the thin, dielectric, sidewall spacers. The heavily doped polysilicon layer is etched back to leave tapered polysilicon sidewall spacers covering the dielectric sidewall spacers. Then dopant is diffused from the polysilicon spacers into the semiconductor substrate to form source and drain regions underlying the polysilicon sidewall spacers. The polysilicon spacer on an end of the gate electrode is removed to separate the polysilicon spacers into a source polysilicon spacer and a drain polysilicon spacer thereby completing formation of a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device. The raised source/drain regions of Pan et al U.S. Pat. No. 6,566,208 are narrow and tapered with the lightly doped regions extending far to the sides. There is very little surface area on the RSD (raised source/drain) regions for making contact connections and the surface is sloped rather than level.
U.S. Pat. No. 6,727,135 of Lee et al. entitled “All-in-One Disposable/Permanent Spacer Elevated Source/Drain, Self-Aligned Silicide CMOS” describes a CMOS device having silicide contacts that are self-aligned to deep junction edges formed within a surface of a semiconductor substrate as well as a method of manufacturing the device. The CMOS device includes patterned gate stack regions formed on a surface of a semiconductor substrate with L-shaped silicon nitride sidewall spacers formed on the vertical sidewalls thereof. Each nitride spacer has a vertical element on the sidewalls of the stack regions plus a horizontal element that is formed on the substrate abutting the gate stack region. Silicide contacts are located on other portions of the semiconductor substrate between adjacent patterned gate stack regions not containing the horizontal element of the L-shaped silicon nitride spacer. There are no raised source/drain regions and no raised STI regions in the structure of Lee et al. U.S. Pat. No. 6,727,135.
U.S. Pat. No. 6,169,017 of Lee entitled “Method to Increase Contact Area” describes a method for fabrication of a semiconductor device with a modified gate contact area. A conformal first sacrificial layer is formed on the silicon substrate and the gate structure. A second sacrificial layer is formed on the silicon substrate, so that the surface of the second sacrificial layer is lower than the top of the polysilicon gate. Then the exposed sacrificial layer is removed, followed by forming a conformal silicon layer covering the silicon substrate. A sidewall spacer is formed on the gate structure. Using the spacer as a mask, the exposed polysilicon layer is removed to form a side-wing polysilicon layer on both sides of the gate to increase the contact area of the gate. Then the spacer, the second sacrificial layer, and the first sacrificial layer are removed. Silicidation is conducted to form a silicide layer on the gate structure and the two side-wing polysilicon layer to lower the gate contact resistance.
U.S. Pat. No. 6,228,729 of Ni entitled “MOS Transistors Having Raised Source and Drain and Interconnects” describes a process for fabricating a CMOS semiconductor device comprising a gate electrode with a raised source/drain structure and with an interconnect inlaid into isolation region. The process comprises the following steps. Form a first dielectric layer and a first conductor layer on the substrate. Form one or more inset isolation regions in the substrate. Fill each inset isolation region with an isolation layer. Form a second dielectric layer on top of the first conductor layer and the isolation layers. Form a first and a second trench simultaneously. Form cavities at the bottom of the first trench. Fill each cavity with a second conductor layer. Form dielectric sidewalls and a dielectric bottom layer in the first trench. Form the gate electrode and an interconnect by filling the first and second trenches with a third conductor layer. Dope the first conductor layer. Then form the raised source/drain by driving the dopant into the surface region of the substrate.
Beyond the 65 nm node of the CMOS technology roadmap, the requirements for gate polysilicon line spacing and source/drain spacer dimension make it increasingly difficult to land contacts effectively between the tightly spaced lines. Removal of silicon nitride spacers is being considered but does not effectively address the problem of making good electrical contacts. This is because the area opened up by removing the nitride spacer is still covered by a thin oxide etch-stop layer that will prevent an electrical connection in that area.
Removal of this thin oxide etch-stop layer before forming the contacts poses a different problem. In this case, the usual contact hole etching process would have to stop abruptly on the silicon surface over the shallow source/drain extension. If it did not stop abruptly enough, then it would etch through the shallow diffusion and cause an electrical short circuit across the junction of the device thereby resulting in very high junction leakage.
Current contact etching processes are designed to stop on the metal silicide material that is formed over the source/drain regions. This silicide does not extend over the extension regions. Attempts to form silicide over the extension regions lead directly to high junction leakages, since the silicide penetrates to a depth that is deeper than the extension diffusion depth.
The design objective it to have the contact etch-stop on the top surface of a silicide layer above the doped silicon of the raised source/drain regions to provide a good processing margin for a high quality contact. Without such an intermediate silicide layer, there is potential for the overetching the contact hole being formed in the device down into the silicon therebelow and punching through one or more of the shallow extension regions (i.e. the LDD/LDS regions) into the active area of the silicon substrate.
If the contact etch were to stop on a silicon oxide layer as well as a silicide layer, then high contact resistance would be a problem since part of the contact be made to the silicon oxide which is an electrical insulator.